1. Field of the Invention
The present invention relates to sense amplifiers used in a programmable logic device (PLD) to implement wide or multiple input NOR gates which operate at high speeds. More particularly, the present invention relates to the product term, or connection, of array cells in the PLD to the sense amplifiers.
2. Description of the Related Art
FIG. 1 shows an array structure for a typical prior art programmable array logic (PAL) device, a type of PLD. The PAL of FIG. 1 has six inputs I.sub.0-5 and four outputs O.sub.0-3. The PAL device further has an AND array 100 followed by a fixed OR array 102. An input such as I.sub.0 to the PAL has a true output 104 and a complement output 106 forming rows connected to array cells 108 containing individual cells, such as 110. An array cell, such as cell 110, may be programmed to be connected or disconnected to an AND gate in the AND array 100. A group of array cells which may be connected to an AND gate as shown at 112 is called a product term.
Although connections from the array cells 108 to the fixed OR array 102 are shown as fixed, they may be programmable. Additional programmable features may also be added, such an output macro cell 114 which is programmable to allow an output to be either registered or combinatorial. The output macro cell 114 is utilized on the AmPALCE22V10 manufactured by Advanced Micro Devices, Inc.
Although shown as an AND array 100, in reality the AND array 100 has AND gates implemented using NOR gates with true and complement row connections to array cells 108 reversed internally.
To implement a multiple input NOR gate, also termed a wide NOR gate, and provide sufficient output voltage to the OR gate array 102, manufacturers utilize sense amplifiers. Sense amplifiers convert a small voltage change from the product term into a larger, rail to rail, voltage to supply to an OR gate at high speed.
FIG. 2 shows a prior art sense amplifier 200 connected to receive a single product term from array cells 202 in a PLD. This sense amplifier configuration was utilized in the AmPALCE16V8 manufactured by Advanced Micro Devices, Inc. to implement a wide NOR gate.
As shown in FIG. 2, array cells 202 receive input signals from rows 1-3 and are connected to form a product term (PT) line connection to sense amplifier 200. Further, the array cells have ground lines connected to form a product term ground (PTG) line connection to sense amplifier 200.
In operation, the PT line will be high if all of the cells are off, or not conducting. The PT line will be low if one or more cells are on, or conducting. A cell will conduct if it is programmed and if its associated row line is high.
The sense amplifier 200 includes an amplifier 204 consisting of two inverters, a first inverter including transistors 206 and 208, and a second inverter including transistors 210 and 212. A voltage clamp consisting of transistors 214 and 216 provides feedback from the input of the second inverter to the input of the first inverter. The input of the amplifier is connected to the PT line of the array cells 202. The circles on transistors, such as 206, 210 and 216, indicate a P-type transistor, while no circle on a transistor indicates an N-type transistor.
The sense amplifier 200 additionally includes a current source transistor 218 controlled by a voltage reference VBSPRP to supply current at the PT line connection to the amplifier input. A PTG current sink transistor 220 controlled by a voltage reference VSARF1 is connected to the PTG line connection to the array cells 202.
In operation, when all cells are off, the current source 218 with current limited by reference voltage VBSPRF will provide current to pull the PT line up until node 250 is driven sufficiently low so that current sunk by clamp transistor 216 just balances the current sourced by current source 218. A low at node 250 will result in a high at SAOUT by means of inverter 210, 212.
The clamp 214, 216 is provided since the PT line has a high capacitance due to the number of cells connected to it. With the high capacitance of the PT line, by limiting the voltage swing to small displacements around the threshold of the amplifier utilizing a clamp 214, 216 higher speeds are provided.
When one or more cells turn on, the PT line will be pulled low. The PTG current sink transistor 220 will then function as a current sink. Reference voltage VSARF1 is a current limiting voltage such that current sink transistor 220 can sink more current than sourced by current source transistor 218. Clamping is provided during turn on so that the PT line voltage will drop until node 250 is sufficiently high that clamp transistor 214 will source just enough current to balance the excess sink capacity of current sink transistor 220. Again, clamping limits the voltage swing to small displacements around the threshold of the amplifier to provide higher output switching speeds.
With the sense amplifier 200 of FIG. 2, performance is limited by the effectiveness of the clamp 214, 216 to limit the voltage swing of the PT line, as well as the slew-rate of the PT line. The slew-rate of the PT line is proportional to the non-equilibrium current driving the product term and inversely proportional to the capacitance of the PT line.